BASEDIR=Val_0x0, TXRXZ=Val_0x0, TESTPORT_SEL=Val_0x0
MIPI-DPHY TX Control Register 0
| BIST_ON | BIST ON |
| BIST_DONE | BIST done |
| BIST_OK | BIST OK |
| CONT_EN | This bit places the PHY in IO continuity test mode. All other PHY control bits should be placed in their default values. |
| TESTPORT_SEL | Test port select 0 (Val_0x0): Select TX_TESTPORT 1 (Val_0x1): Select RX_TESTPORT |
| TXRXZ | Selects master or slave configuration for the PHY. The configuration applies to all the PHY lanes (data and clock). 0 (Val_0x0): Slave-side D-PHY implementation 1 (Val_0x1): Master-side D-PHY implementation |
| BASEDIR | Configures the base direction for PHY data lane 0 (bit [12]) and data lane 1 (bit [13]). 0 (Val_0x0): Configures lane as TX upon startup of the PHY 1 (Val_0x1): Configures lane as RX |
| HSFREQRANGE | Module operating frequency |
| CFGCLKFREQRANGE | Input reference clock frequency |